A large number of lateral DMOS transistor constructions are known both for use as a high-voltage device with a drain voltage of more than 100 V and also for high-frequency power amplification at medium operating voltages, for example in the range of between 10V and 20V. A known type of LDMOS constructions uses a stepped gate insulator for reducing the field strength at the drain edge of the control gate. An example is the so-called field gap or thick field drift region arrangements which are particularly suitable for high drain voltages, being described for example in I Yoshida et al, IEDM Techn. Dig. 1997, pages 51-53, and T R Efland et al, IEDEM Tech. Dig. 1998, pages 679-682. The latter construction however cannot be readily scaled with typical field oxide thicknesses of about 0.5 μm for very high limit frequencies (length of the drift region <0.5 μm for f1>20 GHz) and it is only limitedly compatible with a standard CMOS technology.
In particular, doping of the edge areas of the field region gives rise to problems in spite of an additional lacquer mask for a LDD implantation under the field region when dealing with modern insulation techniques, for example when employing the so-called ‘shallow trench’ technology.
Other constructions, instead of the normal thin gate dielectric of the standard transistors, use a separately produced, thicker gate insulator for the DMOS structures in the entire control gate region or in a part thereof, see T R Efland et al, IED Tech. Dig. 1998, pages 679-682, which also involves a considerable degree of additional expenditure and which in the former case additionally reduces the saturation gradient of the transistors. Further known constructions (so-called active gap or low voltage planar arrangements, as described in I Yoshida et al, IEDM Techn. Dig. 1997, pages 51-53, and T R Efland et al, IEDEM Tech. Dig. 1998, pages 679-682) avoid the above-indicated technological disadvantages insofar as they require substantially only the standard CMOS process for the production thereof, but they do not attain an optimum compromise between their drain breakdown voltage, the on resistance (Ron) and the limit frequency. In particular there is greater difficulty in ensuring adequate long-term stability as a consequence of increased hot electron effects due to excessively high field strengths at the gate edge at the drain side.
It was recently proposed that doping of the LDD region in the drift space should be stepped by what is referred to as a split LDD process, with the LDD doping being reduced in that case of the proximity of the gate edge to such an extent that in that region, with an adequate drain voltage, complete depletion of free charge carriers is achieved and as a result the hot electron effect and the drain/gate capacitance are reduced, see S Xu et al, IEDM Tech. Dig. 1999, pages 201-204. That proposal however at any event requires an additional lacquer mask in comparison with the CMOS standard process. In spite of that measure the on resistance Ron is comparatively high due to the necessarily extremely low level of LDD doping in the proximity of the gate and simultaneous realisation of optimised HF-DMOS transistors together with DMOS transistors for very high drain breakdown voltages (>100 V) and a low on resistance Ron is not possible as a consequence of the higher doping at the drain side of the LDD region which cannot be depleted.
The object of the invention is to eliminate the above-indicated disadvantages of the state of the art and to propose a CMOS-compatible DMOS transistor and method of producing such a transistor, which can be designed by virtue of a suitable layout configuration optionally for very high drain voltages or for power amplification at very high frequencies and which can be produced at a low level of additional cost in comparison with a conventional sub-μm production technology for CMOS circuits. At the same time, without the production cost being increased, the aim is to provide that the product of on resistance Ron and drain-gate capacitance is reduced, for a given breakdown voltage.